The binary number representation has dominated digital logic for decades due to its compact storage requirements. However, since the number system is positional, it needs to “unpack” bits, perform computations, and repack the bits back to binary (e.g., partial products in multiplication). An alternative representation is the unary number system: we use N bits, out of which the €first M are 1 and the rest are 0 to represent the value M /N (essentially base 1 numbers). Stochastic Computing refers to a field in digital logic that generates random unary streams and performs computations on such streams. The streams can be interpreted as probabilities. Such representation would allow for very simple logic to perform complex computations. For example, multiplication of two bit streams X and Y can be done using a single AND gate. In this talk, we will cover early research in Stochastic Computing that dates back to 1960’s, and follow the remarkable evolution of the field to modern methods and applications. Stochastic computing has been used in applications such as image processing, LDPC coding, dynamical system simulations, neural networks and signal processing.

Kiarash (Kia) Bazargan is an Associate Professor in the Electrical and Computer Engineering Department at the University of Minnesota, in the US. He is the chair of the technical program committee of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) in 2018, one of the top conferences in the FPGA field. He has co-authored over 28 papers on the topic of Stochastic Computing, and holds five patents on the subject. He received the B.Sc. degree in Computer Science from Sharif University, Tehran, Iran in 1997, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Northwestern University, Evanston, IL, USA, in 1998 and 2000, respectively. Dr. Bazargan is a Senior Member of the IEEE Computer Society. He was a recipient of the U.S. National Science Foundation Career Award in 2004. He was a Guest Co-Editor of the ACM Transactions on Embedded Computing Systems Special Issue on Dynamically Adaptable Embedded Systems in 2003. He was on the Technical Program Committee of a number of the IEEE/ACM sponsored conferences, including Field Programmable Gate Array, Field Programmable Logic, Design Automation Conference (DAC), International Conference on Computer-Aided Design, and Asia and South Pacific DAC. He was an Associate Editor of the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems from 2005 to 2012.

Despite their remarkable performance in various machine intelligence tasks, the computational intensity of Convolutional Neural Networks (CNNs) has hindered their widespread utilization in resource-constrained embedded and IoT systems. This seminar overviews the landscape of machine intelligence using CNNs, and discusses a number of recent advances in the field that aim to facilitate deployment of trained CNNs to embedded systems with limited compute or energy budgets. In particular, ongoing efforts in the speaker’s research group, which focus on efficient CNN inference using FPGA and Mobile-SoC platforms are discussed in some detail.