Download the Technical Program Schedule in PDF .

Thursday,   December 21, 2017


Welcome Reception


Opening Remarks


Keynote Speech

Professor Soheil Ghiasi, Associate Professor, UC Davis

Deep Convolutional Neural Network in Resource-Constrained
Embedded Systems: How to Fit an Elephant in a Car?


Session 1 & Break


Session1: Embedded Systems


1- M. Tahmasbi, H. Tabatabaee and F. Eltejaei, “Delaunay based two-phase algorithm for connected cover in WSNs”

2- S. Sinaei and O. Fatemi, “Tree-based Design Space Exploration for Mapping Application onto Heterogeneous MPSoCs”

3- P. Esfahani and H. Tabatabaee Malazi, “PAMS: A new position-aware multi-sensor dataset for human activity recognition using

4- G. Korkian, N. Rahmanikia, H. Noori and J. A. Clemente, “Exploration of ring oscillator based temperature sensors network
accuracy on FPGA”


Lunch & Break


Session2: Networks On Chips


1- P. Lotfi-Kamran, M. Modarressi and H. Sarbazi-Azad, “NOC Characteristics of Cloud Applications”

2- R. Akbar and F. Safaei, “A Novel Congestion-aware and Adaptive Routing Algorithm in Mesh-based Networks-on-Chip with Segmentation”

3- M. Ebrahimi, A. Y. Weldezion and M. Daneshtalab, “NoD: Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in
2.5D ICs”


Session3: Reliable/Secure Designs


1- S. Timarchi, M. Abbasi Alaie and H. Kooshkbaghi, “Novel Algorithm and Architectures for High-Speed Low-power Context-based

2- G. Ghasemi, A. M. Hosseini and H. Farbeh, “RI-COTS: Trading Performance for Reliability Improvements in Commercial
Of The Shelf Systems”

3- M. Mushir Ahmed, D. Hely, N. Barbot, R. Siragusa, E. Perret, M. Bernier and F. Garet, “Towards a robust and efficient EM
based authentication of FPGA against counterfeiting and recycling”

4- P. Forouhar and F. Safaei, “DA-FTL: Dynamic Associative Flash Translation Layer”


Friday,   December 22, 2017


Keynote Speech

Professor Kiarsh Bazargan, Associate Professor, University of

Stochastic Computing: A Brief History




Session 4: Emerging Technologies


1- Z. Beiki, M. Tajobian and A. Jahanian, “Efficient Mapping of DNA Logic Circuits on Parallelized Digital Microfluidic Architecture”

2- M. Shahsavari, P. Boulet, A. Shahbahrami and S. Hamdioui, “Impact of Increasing Number of Neurons on Performance of Neuromorphic

3- M. B. Khosroshahy, M. H. Moaiyeri and K. Navi, “Design and Evaluation of a 5-Input Majority Gate-Based Content-Addressable Memory Cell in Quantum-Dot Cellular Automata”


Lunch & Break


Session 5: Parallel and High Performance Computing


1- B. Yarahmadi and F. Khunjush, “Bamshad: A JIT Compiler for running Java Stream APIs on heterogeneous environments”

2- S. N. Basharzad, S. M. Nabavinejad and M. Goudarzi, “A Novel Key Partitioning Schema for Efficient Execution of MapReduce Applications”

3- M. Kiani and A. Rajabzadeh, “SKERD: Reuse Distance Analysis for Simultaneous Multiple GPU Kernel Executions”


4- A. Majd, M. Daneshtalab, J. Plosila, G. Sahebi and E. Troubitsyna, “NOMeS: Near-Optimal Metaheuristic Scheduling for MPSoCs”


Best Paper Announcement & Concluding Remarks